ISRATECH srl

Company Description

ASIC Design House providing you solutions from
Specifications to Silicon

Convert an idea to specifications and SOW
Convert the specs to RTL and test bench
Write the verification suite for the design
Do Synthesis of the RTL to netlist at customer?s technology and generate test vectors
Insertion of JTAG, scan chain and ATPG generation
Layout the netlist at the customer chosen technology
Generate custom library, for simulation, synthesis and layout
Circuit and I/O design at up to 0.13 technology
FPGA to ASIC conversion
Migration of old ASIC designs from obsolete processes to new technologies
Programing in SKILL of Cadence plugin utilities
Writing CAD/CAE SW for ASIC design activities.
Writing scripts and automating tasks.